Oric Schematic Issue 7

Yes, nearly 1 year after the release of the Issue 6.1, I finally made the Issue 7 that would fix the VSYNC problem the previous release had!

What’s new in the Issue 7:

  • There is now a 2 pin header to plug a reset button
  • The hardware VSYNC should now work correctly
  • One of the two ROM socket has been removed to reduce the schematic complexity, but it is now possible to use the original ROM, or any EPROM without the need to change anything on the PCB, because the /ROMDIS signal has been changed!
  • Better, it is now possible, and easily to use a 32K EPROM with the addition of a switch (there are pin on the PCB for this) to select the memory bank.

The licence is still a CC BY-NC-ND (  Creative Commons Licence ), I will keep it until the PCB layout has been finished. I will anyway open a repository on github for the project.

Please use a link to this article instead of the PDF file when you want to share this schematic, as a direct link wont tell the user if a new version would be available.

So here is the Oric Schematic Issue 7

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